1. Field of the Invention
The present invention relates to logic simulation, and more particularly to improvement of accuracy of delay time simulation in a logic circuit.
2. Description of the Related Art
Today, logic simulation is utilized in design of semiconductor integrated circuits including logic circuits. One example of logic simulation is described in IEEE 1986 Custom Integrated Circuits Conference., pp. 456-459.
Logic circuit simulation is used to estimate logic operation in a logic circuit including a plurality of logic elements. In the logic simulation, logic operation is performed corresponding to level ("0" or "1") of one or more input signals in each logic element to calculate the output signal level. As to delay time of one logic element itself, there are methods of measuring the delay time of the logic element in advance, and methods of analyzing an equivalent circuit corresponding to the logic element and calculating the delay time in advance. At the time of executing the logic simulation, the output signal of one logic element is supplied later than the input signal by the delay time of one logic element calculated in advance.
In a conventional method of calculating a delay time from an input terminal of one logic element to an input terminal of a logic element at the succeeding stage in the logic simulation, the total output load capacitance C.sub.T of the logic element is taken into consideration as shown in FIG. 6. As shown in FIG. 7, a relation between the output load capacitance C.sub.T and the delay time is measured or calculated in advance by circuit simulation, and at the time of executing the logic simulation, such delay time provided in advance is utilized.
FIG. 8 is a block diagram of a conventional logic simulator, and FIGS. 9 and 10 are flow charts of the logic simulation using the logic simulator of FIG. 8.
Referring to FIGS. 8 to 10, in step S1 of FIG. 9, information of connection including a plurality of logic elements and capacitances of interconnections, delay time of logic element itself, input signals (test pattern) for testing, control data for simulation (time of analysis and the like), and a table representing relation between the output capacitance and the delay time such as shown in FIG. 6 are input to an input portion 1 of FIG. 8.
In step 2, a control portion 2 sets the analysis time t to 0 and clears an event table 3 before executing simulation. In step S3, the control portion 2 registers output terminals at which input signals have been changed, in comparison between last time and present time, among input terminals for the entire logic circuit in the event table 3. In step S4, the control portion 2 determines whether or not there is an event at present, and if there is any, the simulation proceeds to step S5.
In step S5, an evaluating portion 4 for the logic element calculates an output value corresponding to an input of the logic element at which the event has occurred. In step S6, the evaluating portion 4 for the logic element allots the delay time t.sub.1 of the logic element itself for the logic element at which the event has occurred.
In step S7, a delay time calculating portion 5 calculates total sum C: of the output load capacitance on an output line of the logic element, and determines delay time t.sub.2 based on the table representing the relation between the output load capacitance C.sub.T and the delay time.
In step S8, the control portion 2 registers in the event table 3 that the logic signal changes after the time lapse of (t.sub.1 +t.sub.2) from the present time at an input node of the logic element in the succeeding stage. After step S8, the simulation returns to step S4 in which whether there remains any event which has not yet been simulated at present. If there is any event which has not yet been simulated, simulation again proceeds to step S5. Otherwise, simulation proceeds to step S9 of FIG. 10.
In step S9, the control portion 2 updates simulation time from the present time to the next time. In step S10, the control portion 2 determines whether or not the present time has passed the final time of simulation. If the present time has not yet passed the final time of simulation, the simulation returns to step S3. If the present time has passed the final time of simulation, the control portion 2 provides the result of simulation to an output portion 4 in step S11, and thus the simulation is completed.
In the conventional logic simulation as described above, only the total load capacitance C.sub.T on the output line of the logic element such as shown in FIGS. 6 and 7 is taken into consideration, and resistance component on the output line, capacitance component, and an output impedance circuit including magnitude and arrangement of each of the inductance components are not considered. However, in such a logic circuit as shown in FIG. 11 (for simplicity, inductance component on the output impedance circuit is not shown), the delay time between an input node A of a logic element I and an input node B of a logic element II is estimated to be the same as the delay time between the input node A of the logic element I and an input node C of a logic element III, since only the total load capacitance on the output line of the logic element I is taken into consideration for estimating the delay time in the conventional logic simulation. However, actually the delay time between the nodes A and B is different from that between the nodes A and C, dependent on the connection information including resistance and capacitance on the output line.
As described above, in the conventional logic simulation, influence of the output impedance circuit of the logic element was not accurately taken into consideration, and therefore delay time in a logic circuit could not be estimated with sufficiently high accuracy.